The present invention relates to a semiconductor device including a MOS type transistor and a method of manufacturing the same.
In a MOS type transistor, it was customary to form a metal silicide layer by a self-aligned silicidation technology on the gate electrode and source-drain diffusion layers in order to decrease the resistance of the gate electrode and the source-drain diffusion layers.
As shown in FIG. 16, a P-type silicon substrate 11 includes a region A in which is formed, for example, a memory cell, and a region B in which is formed, for example, a peripheral circuit. A deep trench type capacitor 12 is formed selectively within region A of the silicon substrate 11. A capacitor insulating film 13 is formed around a trench 12a of the capacitor 12. The trench 12a is filled with, for example, a poly-crystalline silicon (polysilicon) to form a storage node 12b. Also, an element isolating region 14 consisting of, for example, a silicon oxide film of an STI (Shallow Trench Isolation) structure is formed within the silicon substrate 11.
In the next step, a gate oxide film 15 is formed on the silicon substrate 11, followed by forming polysilicon gates 16a, 16b, 16c, 16c on the gate oxide film 15. The gates 16a and 16b formed in region A are apart from each other by a distance S3. Also, the 16c and 16d formed in region B are apart from each other by a distance S4. A silicon oxide film 17 is formed to cover the surface of each of these gates 16a, 16b, 16c and 16d. 
Further, an ion implantation and diffusion are carried out by self-alignment with the gates 16a, 16b, 16c and 16d so as to form N-type diffusion layers 18a and 18b having a low impurity concentration in the source-drain regions. Also, the impurity is diffused outward from, for example, the storage node 12b, or an impurity ions are separately implanted, to form a diffusion layer 18c. The diffusion layer 18c acts as a region for reading the charge of the capacitor 12.
In the next step, an insulating film 19 made of, for example, a silicon nitride film having a thickness of, for example, 0.07 xcexcm is formed on the entire surface by chemical Vapor Deposition (CVD) technique, as shown in FIG. 17.
Further, the insulating film 19 is selectively removed by an anisotropic etching to permit the insulating film 19 to remain on the side wall portion of each of the gates 16a, 16b, 16c, 16d, thereby forming a gate side wall insulating film 19a, as shown in FIG. 18.
Then, an ion implantation and diffusion are carried out by self-alignment with the gates 16a, 16b, 16c, 16d and the gate side wall insulating film 19a to form an N-type diffusion layer 20 having an impurity concentration higher than that in the diffusion layers 18a, 18b, thereby forming a MOS transistor of an LDD (Lightly Doped Drain) structure. After formation of the N-type diffusion layer 20, the gate oxide film 15 on the diffusion layer 20 and the silicon oxide film 17 on the upper surface of the gates 16a, 16b, 16c, 16d is removed by a wet etching.
Then, a metal film, e.g., a cobalt thin film, is formed on the entire surface, followed by an annealing treatment to a temperature at which a chemical reaction with silicon takes place. As a result, cobalt silicide films are formed by the reaction between cobalt and silicon in regions where the cobalt thin film is in contact with the gates 16a, 16b, 16c, 16d each containing silicon and with the silicon substrate 11. In this step, a cobalt silicide film is not formed on the gate side wall insulating film 19a in which silicon is covered with the insulating film. Then, the unreacted cobalt film is selectively removed by etching. In this fashion, the cobalt silicide films 22b, 22c are formed on the diffusion layers in regions A and B, and the cobalt silicide film 22a is formed on the upper surface of the gates, as shown in FIG. 19.
Formation of the metal silicide layer such as cobalt silicide films 22b, 22c on the diffusion layers is intended to decrease the resistance of the conductive region of the diffusion layer so as to perform the signal processing at a high speed.
However, if a metal silicide layer is formed on the upper surface of the diffusion layer, a difficulty is brought about that a leak current through the PN junction is increased. Therefore, if a metal silicide layer is formed on the diffusion layer 18a in which the charge of the capacitor 12 is read, the charge holding characteristics of the capacitor 12 are deteriorated. Such being the situation, it is desirable for the cobalt silicide film 22c not to be formed on the diffusion layer 18a. 
To be more specific, it is important to suppress the leak current in order to improve the charge holding characteristics of the capacitor 12 in region A. Also, it is necessary to suppress the resistivity in region B so as to make a high speed operation possible. It follows that it is desirable not to form a cobalt silicide film on the diffusion layer in region A where the leak current should desirably be suppressed.
In the conventional method of manufacturing a semiconductor device described above, however, a cobalt silicide film is unavoidably formed on the diffusion layer where the distances S3, S4 between the gates are larger than twice the thickness T of the silicon nitride film 19, i.e., (S3, S4) greater than 2xc3x97T. Such being the situation, it was impossible to prevent a cobalt silicide film from being formed on the diffusion layer regardless of the thickness T of the silicon nitride film 19.
The present invention, which is intended to overcome the above-noted problems inherent in the prior art, is intended to provide a semiconductor device that permits suppressing the leak current through the PN junction, which is generated under an influence of a metal silicide compound, and which also permits ensuring the signal processing at a high speed, and a method of manufacturing the particular semiconductor device.
According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of forming a gate oxide film on a semiconductor substrate; forming selectively a plurality of first gates a first distance apart from each other and a plurality of second gates a second distance, which larger than the first distance, apart from each other on the gate oxide film; forming a first diffusion layer on the surface of the semiconductor substrate with the first and second gates used as a mask; forming an insulating film having a thickness T1 on the entire surface; etching the insulating film by anisotropic etching to decrease the thickness to T2; etching the insulating film to form a first side wall insulating film on the side wall of each of the first gates, the first side wall insulating film covering that region of the semiconductor substrate which is positioned between adjacent first gates, and to form a second side wall insulating film on the side wall of each of the second gates such that the semiconductor substrate surface positioned between adjacent second gates is exposed to the outside; and introducing an impurity into the surface region of the semiconductor substrate with the first and second gates and the first and second side wall insulating films used as a mask to form a second diffusion layer having an impurity concentration higher than that in the first diffusion layer in that region of the surface of the semiconductor substrate which is positioned between adjacent second side wall insulating films.
The first and second gates and the insulating film are formed to meet the relationship S1xe2x89xa62xc3x97T1 less than S2, where S1 denotes the distance between adjacent first gates, S2 denotes the distance between adjacent second gates, and T1 denotes the thickness of the insulating film as formed.
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of forming a gate oxide film on a semiconductor substrate; forming selectively a plurality of first gates a first distance apart from each other and a plurality of second gates a second distance, which larger than the first distance, apart from each other on the gate oxide film; forming a first diffusion layer on the surface of the semiconductor substrate with the first and second gates used as a mask; forming a first insulating film on the entire surface; selectively removing the first insulating film to form a first side wall insulating film on each of the side walls of the first and second gates to permit that region of the surface of the semiconductor substrate which is interposed between the first and second gate side walls to be exposed to the outside; introducing an impurity into the surface region of the semiconductor substrate by using the first and second gates and the first side wall insulating film as a mask to form a second diffusion layer contiguous to the first diffusion layer and having an impurity concentration higher than that of the first diffusion layer; forming a second insulating film on the entire surface; and etching the second insulating film to form a second side wall insulating film on the side wall of the first side wall insulating film in a manner to cover the surface of the semiconductor substrate and to form a third side wall insulating film on the side wall of the first side wall insulating film in a manner to expose the surface of the semiconductor substrate to the outside.
The first and second gates and the first and second insulating films are formed to meet the relationship S1xe2x89xa62xc3x97(T1+T2) less than S2, where S1 denotes the distance between adjacent first gates, S2 denotes the distance between adjacent second gates, T1 denotes the thickness of the first insulating film as formed, and T2 denotes the thickness of the second insulating film as formed.
It is possible for the method of the present invention to further comprise the step of removing the first side wall insulating film after formation of the second diffusion layer and before formation of the second insulating film, wherein the first and second gates and the first and second insulating films are formed to meet the relationship S1xe2x89xa62xc3x97T2 less than S2, where S1 denotes the distance between adjacent first gates, S2 denotes the distance between adjacent second gates, T2 denotes the thickness of the second insulating film as formed.
According to a third aspect of the present invention, there is provided a semiconductor device, comprising a plurality of first gates formed on a semiconductor substrate a first distance apart from each other; a plurality of second gates formed on the semiconductor substrates a second distance, which is larger than the first distance, apart from each other; a first side wall insulating film formed on the side wall of each of the first gates to fill the clearance between adjacent first gates; a second side wall insulating film formed on the side wall of each of the second gates, the second side wall insulating gates being apart from each other; a first diffusion layer formed on the surface of the semiconductor substrate positioned below the first side wall insulating films; and a second diffusion layer formed on the surface of the semiconductor substrate positioned between adjacent second side wall insulating films.
The first and second gates and the first and second insulating films are formed to meet the relationship S1xe2x89xa62xc3x97T1 less than S2, where S1 denotes the distance between adjacent first gates, S2 denotes the distance between adjacent second gates, T1 denotes the thickness of each of the first and second insulating films.
In the semiconductor device of the present invention, it is possible for the second side wall insulating film to extend over the second diffusion layer.
The present invention provides a semiconductor device that permits suppressing the leak current through the PN junction, which is generated under the influence of the metal silicide compound, and also permits ensuring the signal processing at a high speed, and a method of manufacturing the particular semiconductor device.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.